The HIPEAC Computing Systems Week (CSW) Spring 2022 took place in Tampere (Finland) and focused on Internet of Things (IoT). Experts working in hardware and software optimizations for low-power devices presented state-of-the-art research in these research and insights on future activities. Three keynotes were presented during the event:
- Artificial Intelligence for a more sustainable world, Laura Ruotsalainen (University of Helsinki, Finland)
- Non-cellular 5G for Massive IoT, Teppo Hemiä (Wirepas, Finland)
- RISC-V: Enabling Industrial Acceptance of Open Hardware, Ari Kulmala (Tampere University, Finland)
More details about the event are available at https://www.hipeac.net/csw/2022/tampere/#/.
Keynote summary
The first keynote “Artificial Intelligence for a more sustainable world” by Laura Ruotsalainen (University of Helsinki, Finland) presented sustainability transformation that can be induced with AI research. An AI was defined as a “computer system with adaptive and autonomous features”. In a paper from [Vinuesa, 2020], AI is presented as one of the means to achieve the Sustainable Development Goals (SDGs) from the United Nations. Regrouped under 17 categories, SDGs were introduced in the 2030 Agenda for sustainable development and aim to provide “a shared blueprint for peace and prosperity for people and the planet, now and into the future” (https://sdgs.un.org/goal). In [Vinuesa, 2020], AI is presented as a potential enabler and inhibitor, depending on the targeted SDGs. For example, “AI can enable smart and low-carbon cities encompassing a range of interconnected technologies […], with benefits across SDGs 7, 11, and 13 on climate action”. Laura Ruotsalainen provided insights on the research performed in the Finnish Center for Artificial Intelligence (FCAI) with connections to the SDGs. Different projects were presented such as:
- Virtual laboratories, in the “digital twins” line of thought. Virtualization of experimentation allows better control of the environment while increasing the validation process quality. Research at FCAI includes “Molecular Atmospheric Transformation” and “Sustainable Mobility and Autonomous Systems”.
- AI guided research, where AI is used to find and explore new combinations and designs for optimization. It is used in material research, to find new sustainable materials (e.g. photovoltaic cells). Research in 5G infrastructure locations also uses AI research for optimization purposes.
- Massive data analysis for complex phenomenon modelling. Research in traffic modelling based on air quality using AI to accommodate multi-objectives optimizations.
The second keynote, Non-cellular 5G for Massive IoT” by Teppo Hemiä (Wirepas, Finland), presented solutions for massive IoT connections. With the continuous growth of IoT devices, billions of devices will be added to the current network in the coming years. Certain applications can be referred to as massive IoT networks, with a density of a few thousand devices in a certain area. In a centralized approach, sensors will connect to one base station to return their measurements, an architecture that is hardly scalable once the number of devices rises massively. Instead, Wirepas looks into decentralized networks, where each sensor can act as a base station. This technique, also referred to as multi-hop, allows the continuous additions of new sensors in the network without the need to build a tree-like connection architecture, leading instead to a mesh-like structure. At this point, devices are not bound to be connected to a central network or the internet. Non-cellular 5G, 5G, a.k.a. DECT-2020 NR is now part of the 5G standards, explicitly created for such massive IoT networks. . Similarly to a Local Area Network (LAN), it creates a network of receivers that communicates locally. Applications for such a network of IoT devices are extensive, including asset tracking and smart buildings, with a predicted growth for massive IoT of 125% over 2021-2027.
The third keynote, “RISC-V: Enabling Industrial Acceptance of Open Hardware,” by Ari Kulmala (Tampere University, Finland), presented the opportunities of RISC-V in the current hardware ecosystem. RISC-V is an open Instruction Set Architecture (ISA) based on Reduced Instruction Set Computer (RISC) principles. Contrary to famous ISA like x86 or ARM, RISC-V is open-sourced and free to use and/or modify without any license. In a world where the concept of open hardware is rising more and more, it makes it an attractive choice for both public and private research. Yet, the development of open hardware concepts is not as straightforward as open software. Bugs in hardware have much more significant consequences in costs and are harder to identify, fix and patch. Accountability can be put on the provider in private solutions, but it is not an open solution. Quality is essential at several levels in hardware: CPU core, ease of integration, security, and physical designs. The development of tools and documentation is also crucial. Moreover, the openness of RISC-V is a double edge sword. On the one hand, it offers endless freedom in design, yet on the other hand, it can lead to fragmentation in research and a lack of standardization, making it hard to interface with.
Additional presentations
Besides the keynotes, many researchers presented their current work and project in the domain of hardware/software symbiosis. A few summaries are available below.
“Designing human-centred and trustworthy AI solution: Some learnings from AIGA research project” by Jarkko Malviniemi (Siili Solutions Oy)
This project aims to identify, design, and implement explainable AI solutions for sustainable development. Jarkko explained that the question “Why does this happen in AI?” is still a challenge today. Human-Centered AI (HCAI) is an emerging discipline that aims to create AI systems that amplify and augment human abilities and preserve human control to make AI partnerships more productive, enjoyable, and fair. Moreover, this would lead to “trustworthy AI,” where people would be more inclined to cooperate. SIILI proposes a trustworthy AI framework to find out how people understand AI (https://www.siili.com/).
“RISC-V Virtual Prototyping and Verification” by Vladimir Herdt (University of Bremen)
RISC-V is a free and open instruction set architecture that has huge potential to become a game-changer for modern embedded systems. Virtual prototyping solutions are being developed and introduced into the RISC-V ecosystem to boost the design flow. This talk presented RISC-V Virtual Prototype (VP), a configurable and extensible open-source virtual prototype tailored for RISC-V. RISC-V VP is implemented in standard-compliant SystemC TLM and supports advanced features for software debugging, environment interaction, and operating system integration. Vladimir described a VP as an executable SW mode of an HW system that runs on a host computer. A VP is binary compatible with the Physical HW. VPs are in SystemC and accurate simulation environments for complex embedded SW. The one presented here is based on 32/64 bit core (RV32GC+SUN, RV64GC+SUN), implemented in System/C++ TLM-2.0, and open-source on GitHub (https://github.com/agra-uni-bremen/riscv-vp).
“VEDLIoT Hardware Platforms” by Kevin Mika (Bielefeld University)
Very Efficient Deep Learning for IoT (VEDLIoT) addresses the emerging challenges of the next generation of tactile Internet of Things targeting different objectives, spanning from efficient hardware/software platforms for cognitive IoT devices via a dedicated toolchain enabling secure and robust ML at or near the sensor nodes to validation based on use cases targeting the most relevant application areas. VEDLIoT focuses on modular and highly scalable hardware that enables easy utilization of heterogeneous computing resources at all levels of the computing continuum – from the IoT sensor node via the edge to the cloud. This is enabled by the RECS|Box and t.RECS platforms, which have been expanded towards the cognitive IoT platform u.RECS. This hardware allows seamless integration of heterogeneous processing architectures such as CPUs, GPUs, TPUs (or other application-specific accelerators), and reconfigurable architectures to cope with the highly diverse demands of the IoT domain. It also integrates benchmarking for application characterization, monitoring, and management.
“Collaborative Machine Learning across IoT, Edge, Fog and Cloud devices for Improved Privacy and Resilience” by Setareh Maghsudi (Tübingen University)
Collaborative ML/DL refers to dividing training and/or inference processes over multiple devices and/or locations. Collaborative ML/DL can provide significant benefits in terms of privacy and resilience. At the same time, it comes with many additional operational constraints (maintenance, orchestration), and it is unclear whether it is an obstacle to or an enabler of scaling. Impacts on energy efficiency are also to be assessed. Setareh first highlighted the monolithic aspects of ML today, with the training data centralized in one location and processing. De-centralization offers several benefits, namely privacy, complexity reduction, and training diversity. Yet this comes with challenges, such as the distribution of data and the energetic cost of moving the data depending on the memory type.
“MEEP project: A Digital Laboratory for RISC-V HW/SW Codesign” by Francelly K. Cano Ladino, Barcelona Supercomputing Centre
The MareNostrum Experimental Exascale Platform (MEEP) is an EU financed project, a flexible FPGA-based emulation platform that will explore hardware/software co-design for Exascale Supercomputers and other hardware targets. The project has two major goals: (1) to provide an evaluation platform of pre-silicon IP and ideas, at speed and scale; (2) to Provide a software development and experimentation platform to enable software readiness for new hardware. It will be based on the Accelerated Compute and Memory Engine (ACME). The supercomputer MarreNostrum 5 is under development, with a peak performance of 200 Petaflops. The goal is to provide an experimental platform to create supercomputing technologies “Made in Europe.” More details can be found at https://meep-project.eu/.
“The eProcessor RISC-V HW/SW ecosystem” by Nehir Sonmez, Pedro Trancoso and Kevin Mika
The eProcessor is a 3-year EuroHPC project, which started on April 2021. The Processor project aims to build a new open-source 0o0 processor and accelerators and deliver the first completely open-source European full-stack ecosystem. Processor technology will be extendable (open source), energy efficient (low power), extreme-scale (high performance), suitable for uses in HPC and embedded applications, and extensible (easy to add on-chip and/or off-chip components). The project is an ambitious combination of processor design based on the RISC-V open-source hardware ISA, applications and system software to leverage and extend pre-existing Intellectual Property (IP), combined with new IP that can be used as building blocks for future HPC systems. Currently, Ips are built together with all 10 partners, getting ready for the first tape out by the end of 2022. Two ASIC chips will be produced during the project timeline: one single-core and another multi-core. More details can be found at https://eprocessor.eu/the-eprocessor-ecosystem/.
Acronyms
- AI: Artificial Intelligence
- FCAI: Finnish Center for Artificial Intelligence
- IoT: Internet-of-Things
- ISA: Instruction Set Architecture
- GNSS: Global Navigation Satellite System
- MEEP: MareNostrum Experimental Exascale Platform
- RISC: Reduced Instruction Set Computer
- SDG: Sustainable Developments Goal
- VEDLIoT: Very Efficient Deep Learning for IoT
