Pekka Jääskeläinen

Briefly

Prof. Pekka Jääskeläinen (Computer Engineering): >140 publications; h-index 21. He currently supervises 2 postdocs & 7 PhD candidates as the leader of the Customized Parallel Computing research group. His expertise is in parallel heterogeneous computing software stacks and customized processor hardware design flows. His current research interests include open source tooling to reduce the engineering effort involved in design and program-ming of diverse heterogeneous platforms (CPUs, DSPs, GPUs, ASICs, FPGAs), hardware and compiler techniques to reduce the energy consumption of instruction-set architectures and low latency distributed implementations of HPC algorithms.

Research outputs and activities of the Supervisor

TUNICRIS Research portal Open Researcher and Contributor ID

Research group

The Customized Parallel Computing (CPC) group’s main research focus is on design and programming methodologies of customized parallel computing platforms and real time implementations of challenging algorithms. This includes devices ranging from smallest scale deep edge accelerators to HPC systems. In addition to usual academic contributions, CPC has also made major open source contributions in the field of portable and customized heterogeneous computing: The group has created OpenASIP and Portable Computing Language (pocl) which are being used widely as research platforms and even for product use cases. CPC also created the prototype HIPCL tool which evolved into chipStar, a portable CUDA/HIP implementation using open standards.

Research infrastructure

CPC maintains a 3 node computing cluster for local high performance low latency experimentation. Each of the nodes consist of 2x AMD EPYC 7643 48-Core CPU, 8x NVIDIA RTX A6000 48 GB GPU and RAM: 512 GB DDR4 3200 MHz, which is enough for running local AI training and HPC experiments at lower scale. We also have large FPGAs from the two main vendors to test FPGA portability aspects of our work (AMD/Xilinx Alveo U280 and Altera Bittware IA-420f).